JMB363 SATA DRIVER DOWNLOAD

The second part of the problem is to modify the option ROM given you already know how to configure the chip. Final configuration PATA not enabled because turning it on causes a hang during boot. I think what you want is to change b1 02 to b1 I also used pcicfg in DOS to check the card was detected. The last byte of the file is used as a checksum. Which can be found here: Do i need to fix a checksum value as well?

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Power, Voltage, Temperature, and Frequency.

JMicron JMB363 vs. P35 express SATA controller?

The edits are in x86 machine code. The original bytes were e8 xx xxwhere e8 is sataa opcode for the CALL instruction, and the bit immediate operand is the relative branch target. These configuration registers seem to control the hardware directly. Do i need to fix a checksum value as well?

JMicron JMB vs. P35 express SATA controller? – Ars Technica OpenForum

The bytes b1 02 90 are two x86 instructions mov cl, 0x02; nop; See previous reply. Email will not be published required. It is not a data table containing some form of initial register values. Can you work that changes at latest bios ver 1.

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I used the newest version of the option J,b363 1. Why do you want to avoid the on-board SATA controller? I think what you want is to change b1 02 to b1 Blog Random stuff… Comments Posts.

If so, I would start with the first patched ROM the one that sets df[1: Seems to take values of 0xc2 or 0x Therefore, I chose to set register df[6] to cause the option ROM to quit without detecting drives. I have two HDD conect. Hot-plugging the PCIe card sqta worked for me. Those three bytes used to be a function call to a function that would read a byte from the PCI configuration space register diand return the result in cl.

JMicron JMB Add-on Card AHCI mode « Blog

Those connected at boot were not detected. I have read through this page and start to comprehend the edits needed. You might try looking through the Linux kernel sources to see if the driver for the 88SE gives any clues as to how the chip works…. The release notes hints at the existence of a newer 1. This seems to put the controller in AHCI mode. This changes mov cl, 0x02 to mov cl, 0x Option ROM sets this to either 0xf1 or 0x I want to boot an ide hd from a jmb card.

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Actually, there is only one sata connexion, not two. The bytes that were changed here are x86 code that reads the PCI configuration register and does something with the value.

Unfortunately, the file is quite different. They seem important, causing PCI config register bits 0xed[5: With df[6] set, the option ROM does not detect any disks, despite spending several minutes.

It would be great if you can test it. The sum of all bytes in the file should be 0x They certainly appear to be the same, I have replaced the orom inside the bios of the R3E and the device is now running in AHCI mode.